Introduction

This page is a self-made documentation of the STC8G1K17A from the STC8G family of microcontrollers

STC8G1K17A is a derivative of the then popular Intel 8051 Microcontroller

Device Overview

Core

• Ultra-high speed 8051 Core with single clock per machine cycle, which is called 1T and the speed is about 12 times faster than traditional 8051

• Fully compatible instruction set with traditional 8051

• 13 interrupt sources and 4 interrupt priority levels

• Online debugging is supported

Operating Voltage

• 1.9V~5.5V
• Built-in LDO regulator

Operating Temperature

• -40°C ~ 85°C

Flash Memory

• Up to 17K bytes of Flash memory to be used to store user code

• Configurable size EEPROM, 512bytes single page erased, can be repeatedly erased more than 100 thousand times.

• In-System-Programming, ISP in short, can be used to update the application code, no need for special programmer.

• Online debugging with single chip is supported, and no special emulator is needed. The number of breakpoints is unlimited theoratically.

SRAM

• 128 bytes internal direct access RAM (DATA)
• 128 bytes internal indirect access RAM (IDATA)
• 1024 bytes internal extended RAM (internal XDATA)

Clock

• internal high precise R / C clock (IRC, range from 4MHz to 36MHz), adjustable while ISP and can be divided to lower frequency by user software, 100KHz for instance.

• Error:±0.3% (at the temperature 25°C)

• -1.38% ~ +1.42% temperature drift (at the temperature range of -40°C to +85°C)

• -0.88% ~ +1.05% temperature drift (at the temperature range of -20°C to 65°C)

• Internal 32KHz low speed IRC with large error

Reset

• Hardware Reset
• Power-on reset. Measured voltage value is 1.69V ~ 1.82V. (Effective when the chip does not enable the low voltage reset function)

The power-on reset voltage is a voltage range consisting of an upper limit voltage and a lower limit voltage. When the operating voltage drops from 5V / 3.3V to the lower limit threshold voltage of the power-on reset, the chip is in a reset state; when the voltage rises from 0V to the upper threshold voltage of power-on reset, the chip is released from the reset state.

• Reset by reset pin. The default function of P5.4 is I / O port. The P5.4 pin can be set as the reset pin while ISP download.(Note: When the P5.4 pin is set as the reset pin, the reset level is low)

• Watch dog timer reset

• Low voltage detection reset. 4 low voltage detection levels are provided, 2.2V (Measured as 1.90V~2.04V), 2.4V (Measured as 2.30V~2.50V), V2.7 (Measured as 2.61V~2.82V), V3.0 (Measured as 2.90V~3.13V).

Each level of low-voltage detection voltage is a voltage range consisting of an upper limit voltage and a lower limit voltage. When the operating voltage drops from 5V / 3.3V to the lower limit threshold voltage of low-voltage detection, the low-voltage detection takes effect. When the voltage rises from 0V to the upper threshold voltage, the low voltage detection becomes effective.

Software Reset

• Writing the reset trigger register using software

Interrupts

• 13 interrupt sources: INT0(Supports rising edge and falling edge interrupt), INT1(Supports rising edge and falling edge interrupt), INT2(Supports falling edge interrupt only), INT3(Supports falling edge interrupt only), INT4(Supports falling edge interrupt only), timer0, timer1, UART1, ADC, LVD, SPI, I2C, PCA / CCP / PWM

• 4 interrupt priority levels

• Interrupts that can awaken the CPU in clock stop mode: INT0 (P3.2), INT1 (P3.3), INT2 (P3.6), INT3 (P3.7), INT4 (P3.0), T0 (P3.4), T1(P3.5), RXD(P3.0 / P3.2 / P1.6 / P5.4), CCP0(P3.2 / P3.1), CCP1 (P3.3), CCP2 (P5.4 / P5.5), I2C_SDA (P3.3 / P5.5) and low-voltage detection interrupt, power-down wake-up timer.

Digital Peripherals

• 2 × 16-bit timers: timer0, timer1, where the mode 3 of timer0 has the Non Maskable Interrupt (NMI in short) function. Mode 0 of timer0 and timer1 is 16-bit Auto-reload mode.

• 1 high speed UART: UART1, whose baudrate clock may be fast as FOSC / 4

• 3 groups of PCAs: CCP0, CCP1, CCP2, which can be used as capture, high speed output and 6-bits, 7-bits, 8-bits or 10-bits PWM

• SPI: Master mode, slave mode or master / slave automatic switch mode are supported.

• I2C: Master mode or slave mode are supported.

MDU16: Hardware 16-bit Multiplier and Divider which supports 32-bit divided by 16-bit, 16-bit divided by 16-bit, 16-bit by 16-bit, data shift, and data normalization operations.

Analog Peripherals

• 6 Channels (0-5) ultra-high speed ADC with 10Bit precision analog to digital converter, as fast as 500K(500,000 conversions per second)
• DAC (3 Groups of PCA's can be used as DAC)

Pin Configuration

Download SVG

Memory Organization

yet to be completed

Special Function Registers (SFRs)

Yet to be completed

Instruction Set Summary

Yet to be completed

Extra by Author

Overview

This section contains additional materials provided by the me, including logs of changes, a to-do list for future updates, and libraries that may be useful for working with the STC8GK(08/17)A microcontroller.

It might not be the best in class but it works... for a more better and well made library check out Vincent DEFERT's codeberg repository.

Logs

See Logs for a detailed log of changes and updates I made while working on this IC.

To-Do

To-Do list is simply made and put here for my convinince to keep track of what needs to be done in the future.

Logs

Related to Microcontroller

Note: These logs track the STC8G1K17A peripheral implementation.

📅 16 / 02 / 2025

• Peripheral Setup: Recovered PWM and ADC configurations.

• Refactoring: Created separate Header and Source files for ADC and PWM modules to improve project modularity.

📅 22 / 02 / 2025

• PWM Tuning: Fixed custom frequency logic.

• Current Status: Reliable between 0-250 Hz. Performance above this range is currently unstable.

• Servo Control: Successfully controlled a servo motor, though fine-tuning is required.

• Timing Insight: Discovered frequency variation is best handled via Timer0 Overflow.

• Temporary Solution: Initialize Timer0 after PWM Initialization with the required TimePeriod.

• Formula:

  Timer0 timePeriod = 1 / (PWM_freq * 256)
  

  Note: PWM is set to work with Timer0 Overflow pulses.

📅 12 / 03 / 2025

• UART Library: Completed Header and Source files.

• Default: 9600 Baud @ 11.0592MHz.

• PC Link: Successfully sent and received data between the MCU and PC using the STC Programmer UART helper.

• Timer Conflict:

  ⚠️ Warning: UART uses Timer1 and PWM uses Timer0. Using both simultaneously leaves no hardware timers remaining.

📅 23 / 03 / 2025

• I2C Prototype: Slave mode tested on STC8G1K8 using the STC8G1K17A library.
• Issues: Partially successful; encountering blank data packets. Suspect I2C Interrupt timing.

📅 14 / 04 / 2025

• PCA Modes: Tested Software mode and High Speed Pulse Output Mode (HSOM).

• HSOM Logic: Since the counter toggles at a fixed pca_clk / 2^16, I implemented a workaround using interrupts to reset CH and CL registers to (2^16 - ticks) to control frequency.

• IR Protocol: Implemented NEC format timing.

• Current Issue: Signal is accurate but not yet modulated (likely a main loop timing conflict).

📅 13 / 07 / 2025

• I2C Improvements: Added pin-switching functionality.

• Buffer Access: Streamlined RXD buffer access.

  Note: The first byte is currently ignored; using #value as a placeholder.

To-Do

• IR Remote: Use INT3 on pin P5.5 for signal input. Implement Low Power mode to save battery.

• I2C Expansion: Add TXD register access with auto-clearing/sending logic.

• PWM Fix: Update source files to support a wider range of frequencies.

• New Delay Function: Created a delay system that doesn't use standard timers.

  Solution: Used PCA Software Timer.

  Limit: PCA counter is shared; changing CH/CL may affect other PCA modules.

• IR Modulation: Fixed modulation for CCP1 Port in uVision.

  Solution: Manipulated CR (PCA Counter) directly instead of CCAPM1.

  Limit: Affects all PCA modules due to shared counter.

Libraries

Yet to be added